SweetLow

PCI IDs, including Class, Subclass and Protocol like this --- Bus 01, Device 0B, Function 00 - Silicon Image, Inc. RAID Controller --- PCI\VEN_1095&DEV_3112&REV_02&CC_010400

There are special .INFs from RLoew or me for ATA controllers in PCI Native Mode or non-RAID mode of SiI controllers (check what you really have BTW). Sometimes it works without them but it is better with.

Real PCI ATA controllers work in PCI Native mode so usual ESDI_506.PDR will not work. You need something like RLoew's "SATA" patch but IDK does it work for 95.

Yes, it's possible to do this. But 1. it is not clear result as you do calibration of CPU wait loops in one mode (fast with caching) and then use this waits in other mode (very slow without caching). That's why I slow down system before starting Windows, not in running Windows. 2. It is not works always. For example trying to disable WC for non-local buffer in system memory on Radeon PCI-E cards (direct emulation of AGP behaviour) leads to immediate freeze. Because it is DMA working, CPU less involved.

No, processor caching control is not PCI entity. You can use my package for MSR & MTRR processing (and just use MTRR_RST.EXE from it now) or use "CPUSPD cd" for example for disabling caching in CR0 control register.

I booted to DOS prompt and disable cache (two methods used - through MTRRs or through cache control bit in CR0) and then run Windows - for clean result. Booting is painfully slow but possible nonetheless. P.S. AFAIK this does not disable caching of SM area but I can't imaging scenario that can influences HDA controller using.

JFYI. IDK about any other system but now I can say that definitely on my Intel Core gen 10 system I have some other problem than cache coherence and so No-snoop bits in chipset or PCI-E device or elsewhere (or I completely misunderstand all things). To verify this I remembered one test that I used to try to insulate VCACHE problem on newer systems and I just run my system without caching on the processor side at all And lo and behold - nothing changes, the same short loops in the end.

No BSOD, no hardware problem after reboot, but the same short loops on Core gen10 system.

... few days after asking the right, cleared from other factors result of those reading speed

That is the source of problem with original driver. You have to connect your CD-ROM exactly to SATA ports 0-3 (ATA channels 0-1) that only can work in Legacy Mode on this chipset. And on SATA controller and PATA device it is possible too with help of the PATA-SATA converter, but not on addidional PATA controller port on the motherboard as it works in PCI Native Mode always.

Much simpler. All Windows 9x users now is 40+ old by default, no need to verify anything

It is pretty simple as I said. You can see examples in NVMe sources (I don't want to use Windows 98 DDK Libs too). There you will find exactly PageModifyPermissions declaration and macroses to access PTE. And as I said too - feel free to ask me any implementation if you have problem. IDK do you need this, may be you are interested to write code yourself but nonetheless. P.S. It's curious that in the end I do not need any cache control in NVMe but exactly this thread pushed me to know this fact. Conditional defines and abstraction level work well, I assume you know this. But in this project you can simply implement any NT function you need in version for 9x. And yes, as I remember you expressly stated that you restricted your target to 9x now.

Yes. Just to note - I usually do not go to the next problem before solving previous. You asked for few possible allocators of buffers with needed cache attributes but I slightly misunderstand now - did you try any of them? MS right on the link you gave in this thread recommends to use WC buffer and memory barriers. I assume you try to check this variant.

Looks like you have near to zero observation skills That of course tells enough but not in your favor.

There https://rloewelectronics.com/distribute/WDMEX/0.3/ I could not find them. If some other location exists, please, be gentle to point me. MERCURY127 really posted something like such list from some version of WDMEX https://forum.ru-board.com/topic.cgi?forum=62&topic=28114&start=3160#12 , but there is only names.

No. It does not. I did version of WDMSTUB with this implementation, but did not do "SpecifyCache" part as this function mostly used in binaries because in new DDKs MmMapLockedPages (that is really needed) is just implemented as #define of MmMapLockedPagesSpecifyCache. But it is not hard to do this nonetheless. P.S. It is bad idea to use different cache attributes for different linear mappings of the same physical page. If I remember correctly you can even get Machine Check Exception in such situation if it is enabled. P.P.S. WDMHDA-2026-02-27a - 0E exception (BSOD) on the boot. But version 17 corruption of HDA Controller state is not mentioned now.

Implemented or stubbed? There is no such list in WDMEX.ZIP but I remember that saw this list somewere.

HDA driver model in NT is port/miniport. And HDAUDBUS.SYS is port driver.

http://sweetlow.orgfree.com/download/a20alwon.zip - Added option to automatically detect the "always_on" handler. So there are currently two good options for working in automatic mode: 1. An option with /A20CONTROL:OFF by default. 2. An option to automatically detect the "always_on" handler.

Ok. So I assume you are no less than expirienced driver developer. But why did you ask for help then?

Check that this buffer is properly aligned. It's obvious that it works with aligned buffers only as its parameters are pages, not virtual addresses. But IDK is it working for "partial" buffers - when you reserve large buffer ("pool") and then just take small parts from them. And check the real page attrs (from PDE), of course, in case of any trouble. It is not implemented in WDM and is NT specifiс. But it is easy reproducible through _PageReserve + _PageCommitContig + _PageModifyPermissions or (shorter version) _PageAllocate(PAGECONTIG | PAGEUSEALIGN ) + _PageModifyPermissions

I waited that you running the same in ANY case as I asked you this for your problem insulation, not for my curiosity. But no luck.

$2 USB3.0 UHS-I SD Card Reader + UHS-I Samsung 32G SD Card, Windows 98SE, Nvidia NForce2 (the slowest EHCI controller I know) The same on Windows XP.

I always assumed that turning off EHCI controllers in Device Manager gives the same effect. If you reread the statements of topic starter you will find this one: 150 MBytes @ 60 seconds == 2,5 MB/s. It is simply impossible on USB1 controllers (of course if it measured correctly because some OS options can highly distort usual copy procedure time).

1. You should just ask 2. If in your build environment you can call VXD service (it is possible in .SYS too using some library from Windows 98 DDK AFAIK) then you does not need ASM at all. Else tiny stub is needed only. P.S. Now I at my work environment. The needed function is ULONG _cdecl _PageModifyPermissions(ULONG page, ULONG npages, ULONG permand, ULONG permor); and as I said undocumented but official possibility is two PageCommit flags: #define PC_CACHEDIS 0x00100000 /* Allocate uncached pages - new for WDM */ #define PC_CACHEWT 0x00080000 /* Allocate write through cache pages - new for WDM */ UC cache mode == PC_CACHEDIS | PC_CACHEWT (PAT Index = 3) And on processors with PAT support when MTRR.VXD is loaded: WC cache mode == PC_CACHEWT (PAT Index = 1) in the permor parameter. permand can be 0xFFFFFFFF or ~(PC_CACHEDIS | PC_CACHEWT) - no matter as these flags can be set only and can't be reset.