Enable new modes in old AGP card?

**bristols** · October 25, 2010

I have an old Dell Inspiron 3700 Laptop, with 440BX chipset, Pentium 3 500Mhz CPU and ATI Mobility M1 8MB AGP card. I want to know whether it is somehow possible to enable Banked VGA Write Combining (BVGAWC) and Linear Frame Buffer Write Combining (LFBWC) modes for this card under non-DOS-based operating systems.

Apparently in old systems, Intel left the implementation of these modes, and Write Posting (WP), to software/OS developers. Fortunately for DOS and 9x users, there is FastVid, which implements the modes from pure DOS:

http://www.mdgx.com/umb.htm#FAS

However, I've been unable to find a solution for NT-based systems (I use Windows 2000).

Does anyone know of a piece of software that could help?

I use WPCredit on this system to perform a few tweaks at boot time to the PCI Configuration Registers. Does anyone know whether or not I could change something here to enable these modes? I've managed to change three registers successfully, but I'm ignorant about the purpose of many of them. For your information, here is the registers file (PCR) for the 440BX chipset (and thanks in advance!):


PCR(PCI Configration Registers) Editor / WPCREDIT for WIN32
Copyright (c) 1998  H.Oda!

[COMMENT]=Author H.Oda! & Shohei Uchikawa
[MODEL]=440BX AGPset
[VID]=8086:Intel
[DID]=7190:Host to PCI Bridge

(00)=Vendor Identification
(01)=Vendor Identification
(02)=Device Identification
(03)=Device Identification

[04:7]=Address/Data Stepping    (Not implemented)
[04:6]=Parity Error Enable      1=enable  0=disable
[04:4]=Memory Write/Invalidate  0=hardwired to 0
[04:3]=Special Cycle Enable     0=hardwired to 0
[04:2]=Bus Master Enable        1=hardwired to 1
[04:1]=Memory Access Enable     1=hardwired to 1
[04:0]=I/O Access Enable        0=hardwired to 0

[05:1]=Fast Back-to-Back
[05:0]=SERR# Enable             1=enable  0=disable

[06:7]=Fast Back-to-Back        0=hardwired to 0
[06:4]=Capability List          Negative of AGP DIS bit
[07:7]=Detected Parity Error    1=detects in PCI Bus Tr.
[07:6]=Signaled System Error    1=82443BX asserted SERR#
[07:5]=Received Master Abort    Status 1=abort happened
[07:4]=Received Target Abort    Status 1=abort happened
[07:3}=Signaled Target Abort    Status 0=hardwired to 0
[07:2]=DEVSEL# Timing[1:0]      01 = Medium. (hardwired)
[07:1]=(Same as bit2)
[07:0]=Data Parity Detected     0=hardwired to 0

(08)=Revision Identification  02h=B1 Stepping
(0A)=Sub-Class Code           00h=Host Bridge
(0B)=Base Class Code          06h=Bridge Device

[0D:7]=Master Latency Timer[4:0]00000=disable function
[0D:6]=(Same as top)
[0D:5]=(Same as top)
[0D:4]=(Same as top)
[0D:3]=(Same as top)
(0E)=Header Type              01h=hardwired to 01h

[10:7]=12[5]:10[4] hardwired to 0 forces Min APSIZE 4MB
[10:6]=(Same as top)
[10:5]=(Same as top)
[10:4]=(Same as top)
(10:3)=Prefetchable             1=hardwired to 1
(10:2)=Type[1:0]                00=hardwired to 00
(10:1)=(Same as bit2)
(10:0)=Memory Space Indicator   0=hardwired to 0
[11]=12[5]:10[4] hardwired to 0 forces Min APSIZE 4MB
[12:7]=Lower Programmable Base  Address[1:0]
[12:6]=(Same as top)
[12:5]=12[5]:10[4] hardwired to 0 forces Min APSIZE 4MB
[12:4]=(Same as bit5)
[12:3]=(Same as bit5)
[12:2]=(Same as bit5)
[12:1]=(Same as bit5)
[12:0]=(Same as bit5)
[13:7]=Upper Programmable Base  Address[3:0]
[13:6]=(Same as top)
[13:5]=(Same as top)
[13:4]=(Same as top)
[13:3]=Lower Programmable Base  Address[3:0]
[13:2]=(Same as bit3)
[13:1]=(Same as bit3)
[13:0]=(Same as bit3)

[2C]=Subsystem Vendor ID(Lo)  defaults 00h, write once
[2D]=Subsystem Vendor ID(Hi)  defaults 00h, write once
[2E]=Subsystem ID(Lo)         defaults 00h, write once
[2F]=Subsystem ID(Hi)         defaults 00h, write once

[34]=Capabilities Pointer     A0h=AGP_DIS is 1 00h=else

[50:7]=DRAM Data Integrity(Lo)  00=NonECC 01=EC 10=ECC
[50:6]=ECC Diagnostic Mode      1=enable 0=disable(def)
[50:5]=MDA Present
[50:3]=USWC Write Post During IOBridge Access Enable
[50:2]=In-Order Queue Depth     1 = In-order queue = max.
[51:7]=WSC# Handshake Disable   1=MP and uses ext IOAPIC
[51:5]=Host/DRAM Frequency[1:0] 00=100MHz 10=66MHz
[51:4]=(Same as bit5)
[51:3]=AGP to PCI Access        1=enable 0=disable
[51:2]=PCI Agent to Aperture    1=Access disable from PCI
[51:1]=Aperture Access Global   1=enable 0=disable
[51:0]=DRAM Data Integrity(Hi)  00=NonECC 01=EC 10=ECC
[52:2]=HostBus Fast Data Ready  1=enable 0=disable(def)
[52:1]=ECC - EDO static Drive   1=ECC are always driven. 
[52:0]=IDSEL_REDIRECT           1=AD17 0=AD12(def)
[53:7]=SDRAM[7] ECC Support     1=ECC 0=Non ECC
[53:6]=SDRAM[6] ECC Support     1=ECC 0=Non ECC
[53:5]=SDRAM[5] ECC Support     1=ECC 0=Non ECC
[53:4]=SDRAM[4] ECC Support     1=ECC 0=Non ECC
[53:3]=SDRAM[3] ECC Support     1=ECC 0=Non ECC
[53:2]=SDRAM[2] ECC Support     1=ECC 0=Non ECC
[53:1]=SDRAM[1] ECC Support     1=ECC 0=Non ECC
[53:0]=SDRAM[0] ECC Support     1=ECC 0=Non ECC

[57:5]=Module Mode Configuration
[57:4]=DRAM Type[1:0]           00=EDO 01=SDRAM 10=RSDRAM
[57:3]=11=(Reserved)
[57:2]=DRAM Refresh Rate[2:0]   000=disable 001=15.6us
[57:1]=010=31.2us  011=62.4us   100=124.8us 101=249.6us
[57:0]=110=(Reserved)           111=(Reserved)

[58:1]=EDO RASx# Wait State     0=1 tASR 1=2 tASR
[58:0]=EDO CASx# Wait State     0=1 Tasc 1=2 Tasc

[59:5]=PAM[0] Write Enable      0F0000h - 0FFFFFh
[59:4]=PAM[0] Read Enable       0F0000h - 0FFFFFh
[5A:5]=PAM[1] Write Enable      0C4000h - 0C7FFFh
[5A:4]=PAM[1] Read Enable       0C4000h - 0C7FFFh
[5A:1]=PAM[1] Write Enable      0C0000h - 0C3FFFh
[5A:0]=PAM[1] Read Enable       0C0000h - 0C3FFFh
[5B:5]=PAM[2] Write Enable      0CC000h - 0CFFFFh
[5B:4]=PAM[2] Read Enable       0CC000h - 0CFFFFh
[5B:1]=PAM[2] Write Enable      0C8000h - 0CBFFFh
[5B:0]=PAM[2] Read Enable       0C8000h - 0CBFFFh
[5C:5]=PAM[3] Write Enable      0D4000h - 0D7FFFh
[5C:4]=PAM[3] Read Enable       0D4000h - 0D7FFFh
[5C:1]=PAM[3] Write Enable      0D0000h - 0D3FFFh
[5C:0]=PAM[3] Read Enable       0D0000h - 0D3FFFh
[5D:5]=PAM[4] Write Enable      0DC000h - 0DFFFFh
[5D:4]=PAM[4] Read Enable       0DC000h - 0DFFFFh
[5D:1]=PAM[4] Write Enable      0D8000h - 0DBFFFh
[5D:0]=PAM[4] Read Enable       0D8000h - 0DBFFFh
[5E:5]=PAM[5] Write Enable      0E4000h - 0E7FFFh
[5E:4]=PAM[5] Read Enable       0E4000h - 0E7FFFh
[5E:1]=PAM[5] Write Enable      0E0000h - 0E3FFFh
[5E:0]=PAM[5] Read Enable       0E0000h - 0E3FFFh
[5F:5]=PAM[6] Write Enable      0EC000h - 0EFFFFh
[5F:4]=PAM[6] Read Enable       0EC000h - 0EFFFFh
[5F:1]=PAM[6] Write Enable      0E8000h - 0EBFFFh
[5F:0]=PAM[6] Read Enable       0E8000h - 0EBFFFh

[60]=DRAM Row Boundary Addr 0
[61]=DRAM Row Boundary Addr 1
[62]=DRAM Row Boundary Addr 2
[63]=DRAM Row Boundary Addr 3
[64]=DRAM Row Boundary Addr 4
[65]=DRAM Row Boundary Addr 5
[66]=DRAM Row Boundary Addr 6
[67]=DRAM Row Boundary Addr 7
[68:7]=Fixed DRAM Hole Cntl[1:0]01=512-640KB, 10=15-16MB
[68:6]=(Same as top)

[69:7]=DQMB1/CASB1# strength    [1:0] 00=1x 10=2x 11=3x
[69:6]=(Same as top)
[69:5]=DQMA[7:6,4:2,0] strength [1:0] 00=1x 10=2x 11=3x
[69:4]=(Same as bit5)
[69:3]=CKE1/GCKE strength[1:0]  00=1x 10=2x 11=3x
[69:2]=(Same as bit3)
[69:1]=CKE0/FENA strength[1:0]  00=1x 10=2x 11=3x
[69:0]=(Same as bit1)

[6A:7]=CSA1#/RASA1# etc strength0=1x 1=2x
[6A:6]=CSA0#/RASA0# etc strength0=1x 1=2x
[6A:5]=DQMA5/CASA5# strength    [1:0] 00=1x 10=2x 11=3x
[6A:4]=(Same as bit5)
[6A:3]=DQMA1/CASA1# strength    [1:0] 00=1x 10=2x 11=3x
[6A:2]=(Same as bit3)
[6A:1]=DQMA5/CASA5# strength    [1:0] 00=1x 10=2x 11=3x
[6A:0]=(Same as bit1)

[6B:7]=CSB6#/CKE4 strength[1:0] 00=1x 10=2x 11=3x
[6B:6]=(Same as top)
[6B:5]=CSA6#/CKE2 strength[1:0] 00=1x 10=2x 11=3x
[6B:4]=(Same as bit5)
[6B:3]=CSA5#/RASA5# etc strength0=1x 1=2x
[6B:2]=CSA4#/RASA4# etc strength0=1x 1=2x
[6B:1]=CSA3#/RASA3# etc strength0=1x 1=2x
[6B:0]=CSA2#/RASA2# etc strength0=1x 1=2x

[6C:7]=MECC [7:0] strength 2    [1:0] 00=1x 10=2x 11=3x
[6C:6]=(Same as top)
[6C:5]=MECC [7:0] strength 1    [1:0] 00=1x 10=2x 11=3x
[6C:4]=(Same as bit5)
[6C:3]=CSB7#/CKE5 strength[1:0] 00=1x 10=2x 11=3x
[6C:2]=(Same as bit3)
[6C:1]=CSA7#/CKE3 strength[1:0] 00=1x 10=2x 11=3x
[6C:0]=(Same as bit1)

[6D:7]=MAA[13:0] etc strength   [1:0] 00=1x 10=2x 11=3x
[6D:6]=(Same as top)
[6D:5]=MAB[12:11, 9:0]# strength[1:0] 00=1x 10=2x 11=3x
[6D:4]=(Same as bit5)
[6D:3]=MD [63:0] strength 2[1:0]00=1x 10=2x 11=3x
[6D:2]=(Same as bit3)
[6D:1]=MD [63:0] strength 1[1:0]00=1x 10=2x 11=3x
[6D:0]=(Same as bit1)

(71:7)=(Reserved)               default=1Fh
[72:6]=SMM Space Open
[72:5]=SMM Space Closed
[72:4]=SMM Space Locked
[72:3]=Global SMRAM Enable
(72:2)=Compatible SMM Space Base[2] 010=A0000h - BFFFFh
(72:1)=(Same as bit2)
(72:0)=(Same as bit2)

[73:7]=H_SMRAM_EN (H_SMRAME)
[73:6]=E_SMRAM_ERR (E_SMERR)
[73:5]=SMRAM_Cache (SM_CACHE)   forced to 1
[73:4]=SMRAM_L1_EN (SM_L1)      forced to 1
[73:3]=SMRAM_L2_EN (SM_L2)      forced to 1
[73:2]=TSEG_SZ[1:0] (T_SZ)[1:0] 0=128,1=256,10=512,11=1M
[73:1]=(Same as bit2)
[73:0]=TSEG_EN (T_EN)           1=enable SMRAM 0=disable

[74:1]=SDRAM Row Page Size[1:0] (DRB0)00=2K,01=4K,10=8K
[74:0]=(Same as bit1)
[74:3]=SDRAM Row Page Size[1:0] (DRB1)00=2K,01=4K,10=8K
[74:2]=(Same as bit3)
[74:5]=SDRAM Row Page Size[1:0] (DRB2)00=2K,01=4K,10=8K
[74:4]=(Same as bit5)
[74:7]=SDRAM Row Page Size[1:0] (DRB3)00=2K,01=4K,10=8K
[74:6]=(Same as top)
[75:1]=SDRAM Row Page Size[1:0] (DRB4)00=2K,01=4K,10=8K
[75:0]=(Same as bit1)
[75:3]=SDRAM Row Page Size[1:0] (DRB5)00=2K,01=4K,10=8K
[75:2]=(Same as bit3)
[75:5]=SDRAM Row Page Size[1:0] (DRB6)00=2K,01=4K,10=8K
[75:4]=(Same as bit5)
[75:7]=SDRAM Row Page Size[1:0] (DRB7)00=2K,01=4K,10=8K
[75:6]=(Same as top)

[76:7]=SDRAM Mode Select[2:0]   000=Normal SDRAM Op.
[76:6]=(Same as top)            11x=(Reserved)
[76:5]=(Same as top)            else see manual
[76:4]=SDRAMPWR                 0=3DIMM 1=4DIMM
[76:3]=Leadoff Command Timing   0=4 CS# 1=3 CS#
[76:2]=CAS# Latency             0=3 DCLK 1=2 DCLK
[76:1]=SDRAM RAS# to CAS# Delay 0=3 DCLK 1=2 DCLK
[76:0]=SDRAM RAS# Precharge     0=3 DCLK 1=2 DCLK
[77:1]=DRAM Leadoff Timing[1:0] 01=Add clock delay
[77:0]=(Same as bit1)

[78:3]=DRAM Idle Timer[3:0]     0000=0, 0001=2, 0010=4,
[78:2]=(Same as bit3)           0011=8, 0100=16,
[78:1]=(Same as bit3)           0101=32,0110=64,
[78:0]=(Same as bit3)           0111=128 clks, 1xxx=Inf.

[79:7]=Banks per Row (DRB7)     0=2 Banks 1=4 Banks
[79:6]=Banks per Row (DRB6)     0=2 Banks 1=4 Banks
[79:5]=Banks per Row (DRB5)     0=2 Banks 1=4 Banks
[79:4]=Banks per Row (DRB4)     0=2 Banks 1=4 Banks
[79:3]=Banks per Row (DRB3)     0=2 Banks 1=4 Banks
[79:2]=Banks per Row (DRB2)     0=2 Banks 1=4 Banks
[79:1]=Banks per Row (DRB1)     0=2 Banks 1=4 Banks
[79:0]=Banks per Row (DRB0)     0=2 Banks 1=4 Banks

[7A:7]=Power Down SDRAM Enable  1=enable 0=disable
[7A:6]=ACPI Control Register    1=enable 0=disable
[7A:5]=Suspend Refresh Type     1=Self 0=CBR (Refresh)
[7A:4]=Normal Refresh Enable    1=enable 0=disable
(7A:3)=Quick Start Mode         1=enable 0=disable
[7A:2]=Gated Clock Enable       1=enable 0=disable
[7A:1]=AGP Disable (AGP_DIS)    1=AGP disable 0=enable
[7A:0]=CPU reset without PCIRST 1=enable 0=disable

[7B]=Suspend CBR Refresh Rate [7:0]
[7C:4]=Suspend CBR Refresh Rate Auto Adjust 1=enable
[7C:3]=Suspend CBR Refresh Rate [11:8]
[7C:2]=(Same as bit3)
[7C:1]=(Same as bit3)
[7C:0]=(Same as bit3)

[80:1]=Multiple Bit Error (MBE) 1=multi-bit ECC error
[80:0]=Single Bit Error (SBE)   1=single-bit ECC error
[81:7]=Error Address Pointer    [15:12]
[81:6]=(Same as top)
[81:5]=(Same as top)
[81:4]=(Same as top)
[82]=Error Address Pointer    [23:16]
[83]=Error Address Pointer    [31:24]

[90:7]=SERR# on AGP NonSnoopableAccess Outside ofAperture
[90:6]=SERR# on Invalid AGP DRAMAccess
[90:5]=SERR# on AIGATT
[90:4]=SERR# on Receiving TargetAbort
[90:3]=SERR# on Detected ThermalThrottling Condition
[90:2]=SERR# Assertion Mode
[90:1]=SERR# on Receiving Multi-ple-Bit ECC/Parity Error
[90:0]=SERR# on Receiving       Single-bit ECC Error

(91:7)=Multi-bit 1st Error[2:0] (MBFRE) indicates row
(91:6)=(Same as top)
(91:5)=(Same as top)
[91:4]=Multiple-bit ECC Error   Flag (MEF)
(91:3)=Single-bit 1st Row Error [2:0] (SBFRE)
(91:2)=(Same as bit3)
(91:1)=(Same as bit3)
[91:0]=Single-bit (correctable) ECC Error Flag (SEF)

[92:4]=Read thermal Throttling  Condition
[92:3]=Write Thermal Throttling Condition
[92:2]=AGP non-snoopable access outside of Aperture
[92:1]=Invalid AGP non-snoopableDRAM read access
[92:0]=Access to Invalid GraphicApertureTranslation Table

(94:7)=(Reserved)               default=04h
(95:7)=(Reserved)               default=61h
(99:7)=(Reserved)               default=05h

(A0)=AGP Capability ID
(A1)=Next Capability Pointer
(A2:3)=Minor AGP Revision Number[3:0]
(A2:2)=(Same as bit3)
(A2:1)=(Same as bit3)
(A2:0)=(Same as bit3)
(A2:7)=Major AGP Revision Number[3:0]
(A2:6)=(Same as top)
(A2:5)=(Same as top)
(A2:4)=(Same as top)

[A4:1]=AGP Data Transfer Type[1]01=1x 10=2x 11=default
[A4:0]=AGP Data Transfer Type[0]
[A5:1]=AGP Side Band Addressing Supported, hardwired to 1
[A7]=AGP Maximum Request QueueDepth

[A8:1]=AGP Data Transfer Rate[1]00=default 01=1x 10=2x
[A8:0]=AGP Data Transfer Rate[0]
[A9:1]=AGP Side Band Enable     1=enable 0=disable
[A9:0]=AGP Enable               1=enable 0=disable

[B0:7]=GTLB Enable (and GTLB    Flush Control)
[B1:7]=Snoopable Writes In OrderWith AGP Reads Disable
[B1:5]=Graphics Aperture Write- AGP Read Sync. Enable

[B4:5]=Graphics Aperture Size   (APSIZE) 000000=256MB
[B4:4]=Graphics Aperture Size   100000=128MB
[B4:3]=Graphics Aperture Size   110000=64MB
[B4:2]=Graphics Aperture Size   111000=32MB
[B4:1]=Graphics Aperture Size   111100=16MB
[B4:0]=Graphics Aperture Size   111110=8MB 111111=4MB

[B9:7]=Aperture Translation     Table Base [15:12]
[B9:6]=(Same as top)
[B9:5]=(Same as top)
[B9:4]=(Same as top)
[BA]=Aperture Translation     Table Base [23:16]
[BB]=Aperture Translation     Table Base [31:24]

(C8:7)=(Reserved)               default=18h
(C9:7)=(Reserved)               default=0Ch

[CA:7]=CSA0#/RASA0# CSB0#/RASB0#0=66MHz 1=100MHz
[CA:6]=DQMA5/CASA5# Bus Freq    0=66MHz 1=100MHz
[CA:5]=DQMA1/CASA1# Bus Freq    0=66MHz 1=100MHz
[CA:4]=DQMB5/CASB5# Bus Freq    0=66MHz 1=100MHz
[CA:3]=DQMB1/CASB1# Bus Freq    0=66MHz 1=100MHz
[CA:2]=DQMA[7:6,4:2,0]/         CASA[7:6,4:2,0]#
[CA:1]=CKE1/GCKE Bus Freq       0=66MHz 1=100MHz
[CA:0]=CKE0/FENA Bus Freq       0=66MHz 1=100MHz

[CB:7]=CSA7#/CKE3 Bus Freq      0=66MHz 1=100MHz
[CB:6]=CSB6#/CKE4 Bus Freq      0=66MHz 1=100MHz
[CB:5]=CSA6#/CKE2 Bus Freq      0=66MHz 1=100MHz
[CB:4]=CSA5#/RASA5#,CSB5#/RASB5#0=66MHz 1=100MHz
[CB:3]=CSA4#/RASA4#,CSB4#/RASB4#0=66MHz 1=100MHz
[CB:2]=CSA3#/RASA3#,CSB3#/RASB3#0=66MHz 1=100MHz
[CB:1]=CSA2#/RASA2#,CSB2#/RASB2#0=66MHz 1=100MHz
[CB:0]=CSA1#/RASA1#,CSB1#/RASB1#0=66MHz 1=100MHz

[CC:6]=MAA[13:0] etc Bus Freq   0=66MHz 1=100MHz
[CC:5]=MAB[12:11, 9:0]# Bus Freq0=66MHz 1=100MHz
[CC:4]=MD [63:0] Bus Freq Ctrl2 0=66MHz 1=100MHz
[CC:3]=MD [63:0] Bus Freq Ctrl1 0=66MHz 1=100MHz
[CC:2]=MECC [7:0] Bus Freq Ctrl20=66MHz 1=100MHz
[CC:1]=MECC [7:0] Bus Freq Ctrl10=66MHz 1=100MHz
[CC:0]=CSB7#/CKE5 Bus Freq      0=66MHz 1=100MHz

[D0]=BIOS Scratch Pad (BSPAD) [7:0]
[D1]=BIOS Scratch Pad (BSPAD) [15:8]
[D2]=BIOS Scratch Pad (BSPAD) [23:16]
[D3]=BIOS Scratch Pad (BSPAD) [31:24]

[E0:7..3]=Throttle QWord Maximum   (TQM) [4:0]
[E0:6]=(Same as top)
[E0:5]=(Same as top)
[E0:4]=(Same as top)
[E0:3]=(Same as top)
[E0:2]=DRAM Write Throttle Mode [2:0]
[E0:1]=(Same as bit2)           100=Normal Operations
[E0:0]=(Same as bit2)           else=(Reserved)
[E1:7]=Throttle Monitoring      Window (TMW) [2:0]
[E1:6]=(Same as top)
[E1:5]=(Same as top)
[E1:4]=Throttle QWord Maximum   (TQM) [9:5]
[E1:3]=(Same as bit4)
[E1:2]=(Same as bit4)
[E1:1]=(Same as bit4)
[E1:0]=(Same as bit4)
[E2:7]=Throttle Time (TT) [3:0]
[E2:6]=(Same as top)
[E2:5]=(Same as top)
[E2:4]=(Same as top)
[E2:3]=Throttle Monitoring      Window (TMW) [6:3]
[E2:2]=(Same as bit3)
[E2:1]=(Same as bit3)
[E2:0]=(Same as bit3)
[E3:7]=Global QWord Threshold   (GQT) [5:0]
[E3:6]=(Same as top)
[E3:5]=(Same as top)
[E3:4]=(Same as top)
[E3:3]=(Same as top)
[E3:2]=(Same as top)
[E3:1]=Throttle Time (TT) [5:4]
[E3:0]=(Same as bit1)
[E4:7]=Global DRAM Write        Sampling Window [1:0]
[E4:6]=(Same as top)
[E4:5]=Global QWord Threshold   (GQT) [11:6]
[E4:4]=(Same as bit5)
[E4:3]=(Same as bit5)
[E4:2]=(Same as bit5)
[E4:1]=(Same as bit5)
[E4:0]=(Same as bit5)
[E5:5]=Global DRAM Write        Sampling Window [7:2]
[E5:4]=(Same as bit5)
[E5:3]=(Same as bit5)
[E5:2]=(Same as bit5)
[E5:1]=(Same as bit5)
[E5:0]=(Same as bit5)
[E7:7]=Throttle Lock (TLOCK)    1=E0h - EFh is Read Only

[E8:7]=Read Throttle QWord Max  (RTQM) [4:0]
[E8:6]=(Same as top)
[E8:5]=(Same as top)
[E8:4]=(Same as top)
[E8:3]=(Same as top)
[E8:2]=DRAM Read Throttle Mode  [2:0]
[E8:1]=(Same as bit2)           100=Normal Operations
[E8:0]=(Same as bit2)           else=(Reserved)
[E9:7]=Read Throttle Monitoring Window (RTMW) [2:0]
[E9:6]=(Same as top)
[E9:5]=(Same as top)
[E9:4]=Read Throttle QWord Max  (RTQM) [9:5]
[E9:3]=(Same as bit4)
[E9:2]=(Same as bit4)
[E9:1]=(Same as bit4)
[E9:0]=(Same as bit4)
[EA:7]=Read Throttle Time (RTT) [3:0]
[EA:6]=(Same as top)
[EA:5]=(Same as top)
[EA:4]=(Same as top)
[EA:3]=Read Throttle Monitoring Window (RTMW) [6:3]
[EA:2]=(Same as bit3)
[EA:1]=(Same as bit3)
[EA:0]=(Same as bit3)
[EB:7]=Global Read QWord        Threshold [5:0]
[EB:6]=(Same as top)
[EB:5]=(Same as top)
[EB:4]=(Same as top)
[EB:3]=(Same as top)
[EB:2]=(Same as top)
[EB:1]=Read Throttle Time (RTT) [5:4]
[EB:0]=(Same as bit1)
[EC:7]=Global DRAM Read SamplingWindow (GDRSW) [1:0]
[EC:6]=(Same as top)
[EC:5]=Global Read QWord        Threshold [11:6]
[EC:4]=(Same as bit5)
[EC:3]=(Same as bit5)
[EC:2]=(Same as bit5)
[EC:1]=(Same as bit5)
[EC:0]=(Same as bit5)
[ED:5]=Global DRAM Read SamplingWindow (GDRSW) [7:2]
[ED:4]=(Same as bit5)
[ED:3]=(Same as bit5)
[ED:2]=(Same as bit5)
[ED:1]=(Same as bit5)
[ED:0]=(Same as bit5)

[F0:7]=AGP Jam Latch Strength   1=Enable strong pull-down
[F0:6]=AGP Jam Latch Strength   1=Enable weak pull-down
[F1:1]=AGP Jam Latch Strength   1=Enable strong pull-up
[F1:0]=AGP Jam Latch Strength   1=Enable weak pull-up

(F5:7)=(Reserved)               default=F8h
(F8:7)=(Reserved)               default=20h
(F9:7)=(Reserved)               default=0Fh

Edited October 25, 2010 by bristols

**puntoMX** · October 25, 2010

Although I understand most of it (hardware guy here so never did much coding) but this is really specific; I doubt that any one here ever wend so deep into this and it could take time to get a reply here. PM MDGx, he is a guy that could/would know this and ask him to reply in your topic so other could use that info as well .

**bristols** · October 25, 2010

Although I understand most of it (hardware guy here so never did much coding) but this is really specific; I doubt that any one here ever wend so deep into this and it could take time to get a reply here. PM MDGx, he is a guy that could/would know this and ask him to reply in your topic so other could use that info as well .

Will do. Thanks for the suggestion.

**MDGx** · October 26, 2010

I have an old Dell Inspiron 3700 Laptop, with 440BX chipset, Pentium 3 500Mhz CPU and ATI Mobility M1 8MB AGP card. I want to know whether it is somehow possible to enable Banked VGA Write Combining (BVGAWC) and Linear Frame Buffer Write Combining (LFBWC) modes for this card under non-DOS-based operating systems.
Apparently in old systems, Intel left the implementation of these modes, and Write Posting (WP), to software/OS developers. Fortunately for DOS and 9x users, there is FastVid, which implements the modes from pure DOS:
http://www.mdgx.com/umb.htm#FAS
However, I've been unable to find a solution for NT-based systems (I use Windows 2000).
Does anyone know of a piece of software that could help?

I've sent you a PM on this subject.

HTH

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