Question about RAM / mobo speed matching.

[betamax]

So here's the deal. I was completely clueless about the new DDR2 RAM, so I decided to educate myself. I read some articles about picking the right ram speed etc. And here's what I gathered.

Apparently DDR2 RAM uses the same speed chips, but just double pumps them at the cost of latency time. The clock speed on the RAM stick's bus is twice that of the chip.

DDR2-800 RAM uses 200MHz chips. They are double pumped to 400MHz on the RAM bus. At double data rate, this is an effective speed of 800. However, when an Intel CPU has a Front Side Bus of 1066, that is really only a 266MHz signal on the mobo bus itself (the "system clock" speed, or "core clock"). Since the core clock of the mobo is only 266MHz, the bus speed of the RAM must slow down to 266MHz at the RAM bus to match the mobo's clock. So your DDR2-800 is only running at an effective speed of 533. In this case, DDR2-533 would be the optimal choice.

The only reason for getting DDR2-800 would be if you are overclocking your core clock speed of your mobo to 400MHz, to match the 400MHz bus speed of the RAM.

Am I understanding this correctly? Or is there more to it? I read another article that didn't talk about matching core speeds, it just discussed matching the bandwidth (Gb/s) of the FSB with the bandwidth of the RAM. So which is it? Synchronize the core signals, or match the throughputs?

[ripken204]

you are pretty much correct. the only point for spending another 100-200$ for higher speed ram is for overclocking. just makes it way easier. no point in getting it for normal use.

[betamax]

Here's the part that confuses me:

At 1066MHz FSB, your transfer rate will be 8.528MB/s (1066 instructions per second x 64 bits per instruction x 8 bits per byte)

DDR2-533 has a transfer rate of only half of that: 4.264MB/s. The core speeds are matched (266MHz). But the RAM will still be the bottleneck. This is because intel chips are quad pumped, sending 4 instructions in one cycle (hence the effective 1066 FSB). If one were to get DDR2-1066RAM, the core clock speed of the RAM bus would be 533MHz which is faster than the mobo's 266MHz, but the data transfer rates would be equal.

Would the core speed of the ram bus slow down to 266MHz? Or will it remain at 533MHz? If it remained at 533MHz, it would send two signals every cycle. Once at the high, once at the low. Does the mobo still fetch at the quad pumped rate? Once at the high, once at the first zero, once at the low, once at the second zero. If so, will the instructions at the high and low of the twice as fast 533MHz line up with the instructions at the high, 0, low, 0 of the slower 266MHz? That would maintain the 8.528MB/s transfer rate. Is this even electronically possible? It's a little rusty in my EE courses, but I thought the frequency has to be the same throughout the entire circuit. However if this is possible, I suppose it would look like:

533 MHz Hi Lo Hi Lo Hi Lo etc.

1066MHz Hi 0 Lo 0 Hi 0 etc.

I suppose this is why new chipsets for Intel CPUs support dual channel. DDR2-533 RAM in a dual channel configuration would run at twice the transfer rate. In that case, but the core clocks would be matched, as well as the transfer rates.

Discuss.